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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-22 22:16:45 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-25 19:51:55 +0200
commit4488d7371a2b05e8f1f6952cc969821dfcd4ce42 (patch)
tree97d8f63aa6c262930708ce88ab2dbe1e4ec8088b /src/lib
parent7501b6c285cb8b4f75d3197f8571127a0ad9d504 (diff)
downloadcoreboot-4488d7371a2b05e8f1f6952cc969821dfcd4ce42.tar.xz
nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change
When more than one DIMM is installed on a DCT, only the first DIMM delay values are scaled to the new memory clock frequency after a memory clock change during write leveling. Store the previous memory clock of each DIMM during write leveling to ensure that every DIMM has its delay values rescaled. Change-Id: I56e816d3d3256925598219d92783246f5f4ab567 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
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