diff options
| author | Martin Roth <martinroth@chromium.org> | 2020-01-21 09:28:40 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:48:21 +0000 |
| commit | a616a4be366c6af1f8ccfbfd1f16a4572c7e6c91 (patch) | |
| tree | 1b890c4afbb9047482c19db93dd3ddadd2f76c65 /src/lib | |
| parent | 4cc2cacd333de4d77809f1212e879e61ff8e1616 (diff) | |
| download | coreboot-a616a4be366c6af1f8ccfbfd1f16a4572c7e6c91.tar.xz | |
src/device: Add option to look at revision in option roms
AMD's Family 17h SOCs have the same vendor and device IDs for
their graphics blocks, but need different video BIOSes. The
only difference is the revision number.
Add a Kconfig option that allows us to add the revision number
of the graphics device to the PCI option rom saved in CBFS.
Because searching CBFS takes a non-trivial amount of time,
only enable the option if it's needed. If it's not used, or
if nothing matches, the check will fall through and search for
an option rom with no version.
BUG=b:145817712
TEST=With surrounding patches, loads dali vbios
Change-Id: Icb610a2abe7fcd0f4dc3716382b9853551240a7a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/2013181
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/cbfs.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index b8f3d5cb61..4f0b443360 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -159,6 +159,12 @@ static inline int tohex4(unsigned int c) return (c <= 9) ? (c + '0') : (c - 10 + 'a'); } +static void tohex8(unsigned int val, char *dest) +{ + dest[0] = tohex4((val >> 4) & 0xf); + dest[1] = tohex4(val & 0xf); +} + static void tohex16(unsigned int val, char *dest) { dest[0] = tohex4(val >> 12); @@ -177,6 +183,17 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); } +void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev) +{ + char name[20] = "pciXXXX,XXXX,XX.rom"; + + tohex16(vendor, name + 3); + tohex16(device, name + 8); + tohex8(rev, name + 13); + + return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); +} + size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, uint32_t type) { |