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authorAaron Durbin <adurbin@chromium.org>2015-10-14 10:08:10 -0500
committerJulius Werner <jwerner@chromium.org>2015-11-07 03:28:06 +0100
commit8c8e2b7e4c5f1e6a543ce67cf8b47e9feb1bac50 (patch)
tree6ba073716a547d07ce4f762a31f340b36870ef8b /src/lib
parenta62191b827411e0e42ac64cf42a861f649b874f9 (diff)
downloadcoreboot-8c8e2b7e4c5f1e6a543ce67cf8b47e9feb1bac50.tar.xz
arm64: remove secmon
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/lib')
-rw-r--r--src/lib/Makefile.inc3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index e9f36f6768..7b90819c57 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -164,14 +164,12 @@ bootblock-y += version.c
romstage-y += version.c
ramstage-y += version.c
smm-y += version.c
-secmon-y += version.c
verstage-y += version.c
$(obj)/lib/version.bootblock.o : $(obj)/build.h
$(obj)/lib/version.romstage.o : $(obj)/build.h
$(obj)/lib/version.ramstage.o : $(obj)/build.h
$(obj)/lib/version.smm.o : $(obj)/build.h
-$(obj)/lib/version.secmon.o : $(obj)/build.h
$(obj)/lib/version.verstage.o : $(obj)/build.h
romstage-y += bootmode.c
@@ -181,7 +179,6 @@ bootblock-y += halt.c
romstage-y += halt.c
ramstage-y += halt.c
smm-y += halt.c
-secmon-y += halt.c
ifneq ($(CONFIG_ARCH_X86),y)
# X86 bootblock uses custom ldscripts that are all glued together,