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| author | Vadim Bendebury <vbendeb@chromium.org> | 2011-09-30 12:02:18 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-03-29 20:15:06 +0200 |
| commit | 3e31600e62a260c377ac67b305530a5e93c07051 (patch) | |
| tree | 49a2272ee4badae489eea15770b4e26f5f8503f0 /src/lib | |
| parent | 1078c67af1228a556b1c5c182e8616271f6b7919 (diff) | |
| download | coreboot-3e31600e62a260c377ac67b305530a5e93c07051.tar.xz | |
CBMEM CONSOLE: Enable coreboot CBMEM console.
The appropriate Makefiles are modified to include the required
source code in compilation.
Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/722
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index db640dc005..45cb7887a0 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c @@ -34,6 +35,7 @@ ramstage-y += clog2.c ramstage-y += cbmem.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c |