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authorKane Chen <kane.chen@intel.com>2017-10-16 19:40:18 +0800
committerAaron Durbin <adurbin@chromium.org>2017-10-31 15:49:55 +0000
commit66f1f382cd3bd5a7250e0a7ad35d9a1c505de47a (patch)
tree899e5780ab5d63b9e8d4a6d9402fe0d3f8f4c9e8 /src/lib
parentdfd2a8b7e7bba6ccffb141f812f70b5bc608f37a (diff)
downloadcoreboot-66f1f382cd3bd5a7250e0a7ad35d9a1c505de47a.tar.xz
intel/common/smbus: increase spd read performance
This change increases the spd read performance by using smbus word access. BUG=b:67021853 TEST=boot to os and find 80~100 ms boot time improvement on one dimm Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/lib')
-rw-r--r--src/lib/spd_bin.c28
1 files changed, 21 insertions, 7 deletions
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index b5ab9b7db1..79bda1ef77 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -125,26 +125,40 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index)
CONFIG_DIMM_SPD_SIZE);
}
-static void get_spd(u8 *spd, u8 addr)
+static void smbus_read_spd(u8 *spd, u8 addr)
{
u16 i;
- if (smbus_read_byte(0, addr, 0) == 0xff) {
+ u8 step = 1;
+
+ if (IS_ENABLED(CONFIG_SPD_READ_BY_WORD))
+ step = sizeof(uint16_t);
+
+ for (i = 0; i < SPD_PAGE_LEN; i += step) {
+ if (IS_ENABLED(CONFIG_SPD_READ_BY_WORD))
+ ((u16*)spd)[i / sizeof(uint16_t)] =
+ smbus_read_word(0, addr, i);
+ else
+ spd[i] = smbus_read_byte(0, addr, i);
+ }
+}
+
+static void get_spd(u8 *spd, u8 addr)
+{
+ if (smbus_read_byte(0, addr, 0) == 0xff) {
printk(BIOS_INFO, "No memory dimm at address %02X\n",
addr << 1);
/* Make sure spd is zeroed if dimm doesn't exist. */
memset(spd, 0, CONFIG_DIMM_SPD_SIZE);
return;
}
+ smbus_read_spd(spd, addr);
- for (i = 0; i < SPD_PAGE_LEN; i++)
- spd[i] = smbus_read_byte(0, addr, i);
/* Check if module is DDR4, DDR4 spd is 512 byte. */
if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
- CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) {
+ CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
/* Switch to page 1 */
smbus_write_byte(0, SPD_PAGE_1, 0, 0);
- for (i = 0; i < SPD_PAGE_LEN; i++)
- spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i);
+ smbus_read_spd(spd + SPD_PAGE_LEN, addr);
/* Restore to page 0 */
smbus_write_byte(0, SPD_PAGE_0, 0, 0);
}