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| author | Werner Zeh <werner.zeh@siemens.com> | 2015-10-07 13:34:39 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2015-10-08 04:45:05 +0000 |
| commit | 8a75d82fa5b3abb2473f207554454d9517ca5acb (patch) | |
| tree | 1516c921ef31e9f70d536a4cf5667e5cc9f6936d /src/lib | |
| parent | 37a5d15da92a9fb8a682a32ef1eaf37734fcc5ad (diff) | |
| download | coreboot-8a75d82fa5b3abb2473f207554454d9517ca5acb.tar.xz | |
fsp1_0: Fix broken logic when searching for FSP
Commit 47818b4d6017b89e398cfbc86e3c437e0f81cfdf
(fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO)
breaks the logic which decides whether FSP
could be found or not in cache_as_ram.inc.
Fix the error by inverting the logic of the test.
TEST=Bootet mc_tcu3 board
Change-Id: I993d3422ac406d204a53e4dc890210fb9a52469d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/lib')
0 files changed, 0 insertions, 0 deletions