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| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-04 14:04:47 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:15:20 +0200 |
| commit | 85654a66504f2c87f129d3c414995be4b6cdc09f (patch) | |
| tree | eb65761f5881029a2877a909aab140f6f95aba03 /src/lib | |
| parent | c5b91d6800872268c9f92b13465bf3769d3631e1 (diff) | |
| download | coreboot-85654a66504f2c87f129d3c414995be4b6cdc09f.tar.xz | |
skylake: set DISB in GEN_PMCON_A register properly
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM
training is complete. However, as a 8-bit write was
being performed the bit was never being set.
BUG=chrome-os-partner:43516
BRANCH=None
TEST=Built and booted to kernel. Rebooted. Noted full memory
training was not being peformed.
Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290337
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11183
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/lib')
0 files changed, 0 insertions, 0 deletions