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| author | Furquan Shaikh <furquan@google.com> | 2019-06-01 14:44:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-04 11:20:42 +0000 |
| commit | fca7c4d614eeee1b040cfeba37599b32d0ad55f1 (patch) | |
| tree | af017cdc1552f05e57026ed604b4aadfd2b92ba0 /src/lib | |
| parent | a99ed13e3397bc536012120aab8cadb827913863 (diff) | |
| download | coreboot-fca7c4d614eeee1b040cfeba37599b32d0ad55f1.tar.xz | |
mb/google/hatch: Enable LTR for PCIe ports
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2
BUG=b:134195632
TEST=Verified L1 substate with lspci on hatch:
Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib')
0 files changed, 0 insertions, 0 deletions