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| author | Balaji Manigandan B <balaji.manigandan@intel.com> | 2017-06-09 14:31:42 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-18 19:21:24 +0000 |
| commit | 67716456785f0bfa54f76cfb49396d091892f440 (patch) | |
| tree | 9f0a88c6c567c2204f3937aebc91915d937a6dad /src/lib | |
| parent | 935ff1b208e5e891f1985235b6b4d9518da92f33 (diff) | |
| download | coreboot-67716456785f0bfa54f76cfb49396d091892f440.tar.xz | |
KBL: Update FSP headers - upgrade to FSP 2.5.0
Additional UPDs included with FSP 2.5.0:
FspsUpd.h:
*SataRstOptaneMemory
*Additional Upds for Core Ratio limit
FspmUpd.h:
*RingDownBin
*PcdDebugInterfaceFlags
*PcdSerialDebugBaudRate
*PcdSerialDebugLevel
*GtPllVoltageOffset
*RingPllVoltageOffset
*SaPllVoltageOffset
*McPllVoltageOffset
*RealtimeMemoryTiming
*EvLoader
*Avx3RatioOffset
CQ-DEPEND=CL:*388108,CL:*388109
BUG=None
BRANCH=None
TEST=Build and test on Soraka
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: Id31ddd4595e36c91ba7c888688114c4dbe4db86a
Reviewed-on: https://review.coreboot.org/20123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/lib')
0 files changed, 0 insertions, 0 deletions