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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-03-13 17:16:20 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 12:56:01 +0000
commitcb1e386eabfbf2d0851ed58f97d11a7bab431983 (patch)
treee2f5c0ade2e493d464b0d1531d421d6dacd23648 /src/lib
parenta6bff2d8ab4824a95221fda8a3b175c3f4337720 (diff)
downloadcoreboot-cb1e386eabfbf2d0851ed58f97d11a7bab431983.tar.xz
lib/spd_bin: Add LPDDR4X SPD information and DDR5, LPDDR5 IDs
Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/lib')
-rw-r--r--src/lib/spd_bin.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 35bcb4c2c7..f59e187037 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -36,10 +36,11 @@ static bool use_ddr4_params(int dram_type)
case SPD_DRAM_DDR3:
case SPD_DRAM_LPDDR3_INTEL:
return false;
- /* LPDDR3, LPDDR4 and DDR4 share the same attributes */
+ /* Below DDR type share the same attributes */
case SPD_DRAM_LPDDR3_JEDEC:
case SPD_DRAM_DDR4:
case SPD_DRAM_LPDDR4:
+ case SPD_DRAM_LPDDR4X:
return true;
default:
printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
@@ -60,6 +61,12 @@ static const char *spd_get_module_type_string(int dram_type)
return "DDR4";
case SPD_DRAM_LPDDR4:
return "LPDDR4";
+ case SPD_DRAM_LPDDR4X:
+ return "LPDDR4X";
+ case SPD_DRAM_DDR5:
+ return "DDR5";
+ case SPD_DRAM_LPDDR5:
+ return "LPDDR5";
}
return "UNKNOWN";
}