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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-30 12:55:29 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-31 10:35:07 +0000 |
| commit | ea861ce83118217f1f639cd696dbdb8de87f8ccf (patch) | |
| tree | 25995b8c3c974423bd40095cc224db09f904fcdf /src/mainboard/51nb | |
| parent | 61ba3ac92e832259acd831ab6fab2946f57c7035 (diff) | |
| download | coreboot-ea861ce83118217f1f639cd696dbdb8de87f8ccf.tar.xz | |
mb/51nb/x210: restore left USB3 port in devicetree
Was accidentially removed in 6e50849
Change-Id: I090b6bc8863d17412cb1e23ac816c39f479290c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39937
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/51nb')
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 50d217d170..a98dade9b9 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -116,6 +116,7 @@ chip soc/intel/skylake register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) # PL1 override 25W register "tdp_pl1_override" = "25" |