- Modify all of the Opteron motherboards to have a separate logical

  chip for the amdk8/root_complex


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 106 insertions, 104 deletions

diff --git a/src/mainboard/Iwill/DK8S2/Config.lb b/src/mainboard/Iwill/DK8S2/Config.lb
index c28b8d3ca7..661cadcdd2 100644
--- a/src/mainboard/Iwill/DK8S2/Config.lb
+++ b/src/mainboard/Iwill/DK8S2/Config.lb
@@ -130,75 +130,76 @@ dir /pc80
 config chip.h
 
 # config for arima/hdama
-chip northbridge/amd/amdk8
+chip northbridge/amd/amdk8/root_complex
 	device pci_domain 0 on
-		device pci 18.0 on # LDT 0
-			chip southbridge/amd/amd8131
-				device pci 0.0 on end
-				device pci 0.1 on end
-				device pci 1.0 on end
-				device pci 1.1 on end
-			end
-			chip southbridge/amd/amd8111
-				# this "device pci 0.0" is the parent the next one
-				# PCI bridge
-				device pci 0.0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on # LDT 0
+				chip southbridge/amd/amd8131
 					device pci 0.0 on end
 					device pci 0.1 on end
-					device pci 0.2 on end
-					device pci 1.0 off end
+					device pci 1.0 on end
+					device pci 1.1 on end
 				end
-				device pci 1.0 on
-					chip superio/winbond/w83627hf
-						device pnp  2e.0 on      # Floppy
-							 io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp  2e.1 off     # Parallel Port
-							 io 0x60 = 0x378
-							irq 0x70 = 7
-						end
-						device pnp  2e.2 on      # Com1
-							 io 0x60 = 0x3f8
-							irq 0x70 = 4
-						end
-						device pnp  2e.3 off     # Com2
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp  2e.5 on      # Keyboard
-							 io 0x60 = 0x60
-							 io 0x62 = 0x64
-						       irq 0x70 = 1
-							irq 0x72 = 12
-						end
-						device pnp  2e.6 off end # CIR
-						device pnp  2e.7 off end # GAME_MIDI_GIPO1
-						device pnp  2e.8 off end # GPIO2
-						device pnp  2e.9 off end # GPIO3
-						device pnp  2e.a off end # ACPI
-						device pnp  2e.b on      # HW Monitor
-							 io 0x60 = 0x290
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp  2e.0 on      # Floppy
+								 io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp  2e.1 off     # Parallel Port
+								 io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp  2e.2 on      # Com1
+								 io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp  2e.3 off     # Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp  2e.5 on      # Keyboard
+								 io 0x60 = 0x60
+								 io 0x62 = 0x64
+							       irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp  2e.6 off end # CIR
+							device pnp  2e.7 off end # GAME_MIDI_GIPO1
+							device pnp  2e.8 off end # GPIO2
+							device pnp  2e.9 off end # GPIO3
+							device pnp  2e.a off end # ACPI
+							device pnp  2e.b on      # HW Monitor
+								 io 0x60 = 0x290
+							end
+							register "com1" = "{1}"
+						#	register "com1" = "{1, 0, 0x3f8, 4}"
+						#	register "lpt" = "{1}"
 						end
-						register "com1" = "{1}"
-					#	register "com1" = "{1, 0, 0x3f8, 4}"
-					#	register "lpt" = "{1}"
 					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end 
+					device pci 1.5 off end
+					device pci 1.6 off end
 				end
-				device pci 1.1 on end
-				device pci 1.2 on end
-				device pci 1.3 on end 
-				device pci 1.5 off end
-				device pci 1.6 off end
-			end
-		end # LDT0
-		device pci 18.0 on end # LDT1
-		device pci 18.0 on end # LDT2
-		device pci 18.1 on end
-		device pci 18.2 on end
-		device pci 18.3 on end
-
+			end # LDT0
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
 		chip northbridge/amd/amdk8
 			device pci 19.0 on end
 			device pci 19.0 on end
diff --git a/src/mainboard/Iwill/DK8X/Config.lb b/src/mainboard/Iwill/DK8X/Config.lb
index 903f5c6c62..d8fc0cb5e0 100644
--- a/src/mainboard/Iwill/DK8X/Config.lb
+++ b/src/mainboard/Iwill/DK8X/Config.lb
@@ -126,54 +126,55 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/amd/amdk8
+chip northbridge/amd/amdk8/root_complex
 	device pci_domain 0 on
-		device pci 18.0 on #  northbridge 
-			#  devices on link 0, link 0 == LDT 0 
-			chip southbridge/amd/amd8131
-				# the on/off keyword is mandatory
-				device pci 0.0 on end
-				device pci 0.1 on end
-				device pci 1.0 on end
-				device pci 1.1 on end
-			end
-			chip southbridge/amd/amd8111
-				# this "device pci 0.0" is the parent the next one
-				# PCI bridge
-				device pci 0.0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0 
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
 					device pci 0.0 on end
 					device pci 0.1 on end
-					device pci 0.2 on end
-					device pci 1.0 off end
+					device pci 1.0 on end
+					device pci 1.1 on end
 				end
-				device pci 1.0 on
-					chip superio/winbond/w83627thf
-						device pnp 2e.0 on end
-						device pnp 2e.1 on end
-						device pnp 2e.2 on end
-						device pnp 2e.3 on end
-						device pnp 2e.4 on end
-						device pnp 2e.5 on end
-						device pnp 2e.6 on end
-						device pnp 2e.7 on end 
-						device pnp 2e.8 on end 
-						device pnp 2e.9 on end 
-						device pnp 2e.a on end 
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627thf
+							device pnp 2e.0 on end
+							device pnp 2e.1 on end
+							device pnp 2e.2 on end
+							device pnp 2e.3 on end
+							device pnp 2e.4 on end
+							device pnp 2e.5 on end
+							device pnp 2e.6 on end
+							device pnp 2e.7 on end 
+							device pnp 2e.8 on end 
+							device pnp 2e.9 on end 
+							device pnp 2e.a on end 
+						end
 					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end 
+					device pci 1.5 off end
+					device pci 1.6 off end
 				end
-				device pci 1.1 on end
-				device pci 1.2 on end
-				device pci 1.3 on end 
-				device pci 1.5 off end
-				device pci 1.6 off end
-			end
-		end # LDT0
-		device pci 18.0 on end # LDT1
-		device pci 18.0 on end # LDT2
-		device pci 18.1 on end
-		device pci 18.2 on end
-		device pci 18.3 on end
-
+			end # LDT0
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
 		chip northbridge/amd/amdk8
 			device pci 19.0 on end
 			device pci 19.0 on end