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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-08-15 16:28:48 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-09 19:07:34 +0100 |
| commit | a1ea82283d868af3681c3575722753f0789b941d (patch) | |
| tree | b78d98b3e04cd357a7fd4e0339a81dc9da3501d3 /src/mainboard/Kconfig | |
| parent | 0a1c2d62faed99edb5ffb53c2058cc6847568be0 (diff) | |
| download | coreboot-a1ea82283d868af3681c3575722753f0789b941d.tar.xz | |
Make coreboot use the offset parameter in cbfstool create
On Sandybridge and Ivybridge systems the firmware image has to
store a lot more than just coreboot, including:
- a firmware descriptor
- Intel Management Engine firmware
- MRC cache information
This option allows to limit the size of the CBFS portion in
the firmware image.
Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1770
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/Kconfig')
| -rw-r--r-- | src/mainboard/Kconfig | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 779e061b9c..77bfa0f007 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -304,10 +304,14 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 -config CACHE_ROM_SIZE +config CBFS_SIZE hex default ROM_SIZE +config CACHE_ROM_SIZE + hex + default CBFS_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE |