diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-07 16:24:28 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-07 16:24:28 +0000 |
| commit | 6798b478027cb3fd44d52706ad69dee29bae19ba (patch) | |
| tree | a6cb5f73d04d009d7187a1bd0cf65878857166a0 /src/mainboard/a-trend | |
| parent | 6f2d20ec490a276a087acad0b3866c0f3ee844c4 (diff) | |
| download | coreboot-6798b478027cb3fd44d52706ad69dee29bae19ba.tar.xz | |
Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.
Also:
Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.
As an additional benefit this patch also gets rid of one .c file include
in romstage.c.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/a-trend')
| -rw-r--r-- | src/mainboard/a-trend/atc-6220/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/a-trend/atc-6240/romstage.c | 4 |
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index a55997fae9..b32f10b102 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ void main(unsigned long bist) console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index abfe3c4a15..4384c2387f 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ void main(unsigned long bist) console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); |