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| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/mainboard/advansus/a785e-i/Makefile.inc | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
| download | coreboot-feed329a0c006968242aa3065506b5f37f4308d4.tar.xz | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/advansus/a785e-i/Makefile.inc')
| -rwxr-xr-x | src/mainboard/advansus/a785e-i/Makefile.inc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index cf8ec2664c..737bb1c1eb 100755 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -1,8 +1,6 @@ #romstage-y += reset.c #FIXME romstage have include test_rest.c -romstage-y += pmio.c ramstage-y += reset.c -ramstage-y += pmio.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_AMD_AGESA),y) |