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| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/mainboard/advansus/a785e-i/romstage.c | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
| download | coreboot-feed329a0c006968242aa3065506b5f37f4308d4.tar.xz | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/advansus/a785e-i/romstage.c')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/romstage.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 9e31779118..3a33b5fc9c 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -47,7 +47,7 @@ #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include <SbEarly.h> +#include <sb_cimx.h> #include <SBPLATFORM.h> /* SB OEM constants */ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" @@ -82,21 +82,6 @@ void soft_reset(void) outb(0x06, 0x0cf9); } -//FIXME copyed from sb800 -#include <pmio.h> -static void sb800_clk_output_48Mhz(void) -{ - /* AcpiMMioDecodeEn */ - u8 reg8; - reg8 = pm_ioread(0x24); - reg8 |= 1; - reg8 &= ~(1 << 1); - pm_iowrite(0x24, reg8); - - *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ -} - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -112,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init - sb_poweron_init(); + sb_Poweron_Init(); } post_code(0x30); |