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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-24 08:53:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-26 13:38:46 +0200 |
| commit | b87a734771449ed06cd91621da4c893a1ad722b0 (patch) | |
| tree | 9ca49309fba09071aeaab4cecc9e80ed94ca9a0e /src/mainboard/advansus/a785e-i | |
| parent | 8da96e57c89860f429f1bf590c10fa364b8019d4 (diff) | |
| download | coreboot-b87a734771449ed06cd91621da4c893a1ad722b0.tar.xz | |
mainboard/*/*/dsdt.asl: Use tabs for indents
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/advansus/a785e-i')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/dsdt.asl | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 9dfdbb17b9..37b9ae17a5 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -1534,8 +1534,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1578,20 +1578,20 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ |