diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-06-20 17:38:49 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-06-22 01:27:46 +0200 |
| commit | 05a89ab922473f375820a3bd68691bb085c62448 (patch) | |
| tree | 22510d53ab35d80987cb17f2a11ce08039db49a5 /src/mainboard/advansus/a785e-i | |
| parent | ee39ea7e7edf9699f1bae1b2708ad6816f054817 (diff) | |
| download | coreboot-05a89ab922473f375820a3bd68691bb085c62448.tar.xz | |
Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/advansus/a785e-i')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/advansus/a785e-i/romstage.c | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index ab3104bdaa..6e3a4ab528 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select QRANK_DIMM_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 + select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_WINBOND_W83627HF #COM1, COM2 #select SUPERIO_FINTEK_F81216AD #COM3, COM4 select HAVE_BUS_CONFIG diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index 74f50d02fa..25a1f646d8 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -34,7 +34,7 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL end - chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.2 on end # USB @@ -112,7 +112,7 @@ chip northbridge/amd/amdfam10/root_complex #register "gpp_configuration" = "3" #2:1:1:0 register "gpp_configuration" = "4" #1:1:1:1 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx_wrapper/sb800 + end #southbridge/amd/cimx/sb800 end # device pci 18.0 device pci 18.1 on end diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index f2544e70ec..9e31779118 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -49,7 +49,7 @@ #include "southbridge/amd/rs780/early_setup.c" #include <SbEarly.h> #include <SBPLATFORM.h> /* SB OEM constants */ -#include <southbridge/amd/cimx_wrapper/sb800/smbus.h> +#include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) |