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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-08 07:20:48 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-09 23:28:43 +0100
commitf0a13ceb639f7a7d5a6e84a2c89f3deab0de757a (patch)
treea049b25d82afe909b08fa46b4c4ade23f829d29c /src/mainboard/advansus
parent299c26510202faa3cf7383040f330d502d224fdf (diff)
downloadcoreboot-f0a13ceb639f7a7d5a6e84a2c89f3deab0de757a.tar.xz
AMD boards: Fix includes for microcode updates
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/advansus')
-rw-r--r--src/mainboard/advansus/a785e-i/romstage.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 8e7aa40bb0..30616c58c5 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -65,10 +65,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
-#include "cpu/amd/microcode/microcode.c"
-#if CONFIG_UPDATE_CPU_MICROCODE
-#include "cpu/amd/model_10xxx/update_microcode.c"
-#endif
+#include "cpu/amd/microcode.h"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "spd.h"
@@ -126,9 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
-#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
-#endif
+
post_code(0x33);
cpuSetAMDMSR();