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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-04-29 13:09:50 +1000 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-31 21:17:37 +0200 |
| commit | beb0f2631fe6e49e86687cc3a7cf63ce41157a45 (patch) | |
| tree | efafc117389de92204dcbc98e6edd9ad56c2212c /src/mainboard/advansus | |
| parent | 9068788a8f0c96a5153fcd4e5ed80eac80b060c6 (diff) | |
| download | coreboot-beb0f2631fe6e49e86687cc3a7cf63ce41157a45.tar.xz | |
superio/winbond/w83627hf: Avoid .c includes in mainboards
Move towards the removal of the superio model specific xxx_serial_enable
implementation. Make remaining superio romstage parts link-time symbols
and fix corresponding mainboards to match.
The following mainboards remain unconverted as they are ROMCC:
- mainboard/supermicro/x6dai_g
- mainboard/supermicro/x6dhe_g
- mainboard/supermicro/x6dhr_ig
- mainboard/supermicro/x6dhr_ig2
and so block the final removal of w83627hf_serial_enable().
Special cases:
- mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
Provide local superio pnp_ programming entry/exit functions as to avoid
making superio implementation global symbols. Although this is not the
proper/final solution, it does mitigate possible symbol collisions and
allow for continued superio refactorisation.
Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5601
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/advansus')
| -rw-r--r-- | src/mainboard/advansus/a785e-i/romstage.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 490d1465e4..2402798ffd 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); |