diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2007-03-20 13:43:50 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2007-03-20 13:43:50 +0000 |
| commit | 999bc60d5fb76f557c94ff55d753773cdc6bfa1c (patch) | |
| tree | 028264f1914b6d796567f205874cc99a05c5b02a /src/mainboard/agami | |
| parent | 36b601ca3cd46344f844b7ef8fb304958d4091ad (diff) | |
| download | coreboot-999bc60d5fb76f557c94ff55d753773cdc6bfa1c.tar.xz | |
fix a stupid cut and paste error.
This is pretty trivial, as it was correct in the original non-CAR code.
Suddently, CAR works nicely.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/agami')
| -rw-r--r-- | src/mainboard/agami/aruma/cache_as_ram_auto.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/mainboard/agami/aruma/cache_as_ram_auto.c b/src/mainboard/agami/aruma/cache_as_ram_auto.c index 89ef1b1ad6..1fef238dd2 100644 --- a/src/mainboard/agami/aruma/cache_as_ram_auto.c +++ b/src/mainboard/agami/aruma/cache_as_ram_auto.c @@ -64,24 +64,26 @@ static void soft_reset(void) pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); } +/* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), + SMBUS_IO_BASE + 0xc0 + 29); } static void memreset(int controllers, const struct mem_controller *ctrl) { - if (is_cpu_pre_c0()) { - udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); - } + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), + SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } } static inline void activate_spd_rom(const struct mem_controller *ctrl) |