Rename almost all occurences of LinuxBIOS to coreboot.

Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 16 insertions, 16 deletions

diff --git a/src/mainboard/agami/aruma/Config.lb b/src/mainboard/agami/aruma/Config.lb
index c8cdcd8bd5..b327bf651f 100644
--- a/src/mainboard/agami/aruma/Config.lb
+++ b/src/mainboard/agami/aruma/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -145,7 +145,7 @@ else
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 mainboardinit cpu/x86/16bit/entry16.inc
@@ -163,7 +163,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
@@ -193,7 +193,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
diff --git a/src/mainboard/agami/aruma/Options.lb b/src/mainboard/agami/aruma/Options.lb
index 04fff60e3b..47eb59fa7f 100644
--- a/src/mainboard/agami/aruma/Options.lb
+++ b/src/mainboard/agami/aruma/Options.lb
@@ -37,7 +37,7 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
 uses _RAMBASE
 uses CC
 uses HOSTCC
@@ -140,7 +140,7 @@ default ACPI_SSDTX_NUM=3
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -196,10 +196,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0
 
 
 ###
-### LinuxBIOS layout values
+### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -218,7 +218,7 @@ default HEAP_SIZE=0x8000
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
 ##
 default _RAMBASE=0x00004000
 
@@ -262,7 +262,7 @@ default TTYS0_BASE=0x3f8
 default TTYS0_LCS=0x3
 
 ##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
 ##
 ## EMERG      1   system is unusable               
 ## ALERT      2   action must be taken immediately 
@@ -275,7 +275,7 @@ default TTYS0_LCS=0x3
 ## SPEW       9   Way too many details             
 
 
-## These values can be overwritten by LinuxBIOSv2/targets/agami/aruma/Config.lb
+## These values can be overwritten by corebootv2/targets/agami/aruma/Config.lb
 ## Request this level of debugging output
 default  DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
diff --git a/src/mainboard/agami/aruma/acpi_tables_static.c b/src/mainboard/agami/aruma/acpi_tables_static.c
index 3ff0d717c9..b20a7d72e5 100644
--- a/src/mainboard/agami/aruma/acpi_tables_static.c
+++ b/src/mainboard/agami/aruma/acpi_tables_static.c
@@ -83,7 +83,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 /* The next two tables are used by our DSDT and are freely defined
  * here. This construct is used because the bus numbers containing 
- * the 8131 bridges may vary so that we need to pass LinuxBIOS 
+ * the 8131 bridges may vary so that we need to pass coreboot 
  * knowledge into the DSDT
  */
 typedef struct lnxc_busses {
@@ -96,7 +96,7 @@ typedef struct acpi_lnxb {
 	acpi_lnxb_busses_t busses[5];
 } acpi_lnxb_t;
 
-/* special linuxbios acpi table */
+/* special coreboot acpi table */
 void acpi_create_lnxb(acpi_lnxb_t *lnxb)
 {
 	device_t dev;