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authorZheng Bao <fishbaozi@gmail.com>2015-11-18 22:52:37 +0800
committerZheng Bao <zheng.bao@amd.com>2015-11-18 17:02:28 +0100
commit631c8a269006bb8f02860606d35f8d6590954f5e (patch)
treebd7b6fb9c274ec1a807cbd55cd14eb169bcfd4c3 /src/mainboard/amd/bettong/acpi
parent71c0aa29fa83219e76af70dd452b6b2e97e4dfbb (diff)
downloadcoreboot-631c8a269006bb8f02860606d35f8d6590954f5e.tar.xz
AMD/Bettong: add FCH's GPIO, UART & I2C support
Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled by registers mapped at MMIO space. This ASL code is used for Windows drivers. TEST: 1. Boot Windows 8 or Windows 10. 2. Install AMD Catalyst driver. 3. AMD FPIO, UART and I2C can be found in device manager. 4. I2C passed Multi Interface Test Tool (MITT) test. Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11750 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd/bettong/acpi')
-rw-r--r--src/mainboard/amd/bettong/acpi/carrizo_fch.asl101
1 files changed, 101 insertions, 0 deletions
diff --git a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl
new file mode 100644
index 0000000000..5bfb366a49
--- /dev/null
+++ b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device(GPIO) {
+ Name (_HID, "AMD0030")
+ Name (_CID, "AMD0030")
+ Name(_UID, 0)
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ //
+ // Interrupt resource. In this example, banks 0 & 1 share the same
+ // interrupt to the parent controller and similarly banks 2 & 3.
+ //
+ // N.B. The definition below is chosen for an arbitrary
+ // test platform. It needs to be changed to reflect the hardware
+ // configuration of the actual platform
+ //
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+
+ //
+ // Memory resource. The definition below is chosen for an arbitrary
+ // test platform. It needs to be changed to reflect the hardware
+ // configuration of the actual platform.
+ //
+ Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
+ })
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0x0F)
+ }
+}
+
+Device(FUR0) {
+ Name(_HID,"AMD0020")
+ Name(_UID,0x0)
+ Name(_CRS, ResourceTemplate() {
+ IRQ(Edge, ActiveHigh, Exclusive) {10}
+ Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
+ })
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0x0F)
+ }
+}
+
+Device(FUR1) {
+ Name(_HID,"AMD0020")
+ Name(_UID,0x1)
+ Name(_CRS, ResourceTemplate() {
+ IRQ(Edge, ActiveHigh, Exclusive) {11}
+ Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
+ })
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0x0F)
+ }
+}
+
+Device(I2CA) {
+ Name(_HID,"AMD0010")
+ Name(_UID,0x0)
+ Name(_CRS, ResourceTemplate() {
+ IRQ(Edge, ActiveHigh, Exclusive) {3}
+ Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
+ })
+
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0x0F)
+ }
+}
+
+Device(I2CB)
+{
+ Name(_HID,"AMD0010")
+ Name(_UID,0x1)
+ Name(_CRS, ResourceTemplate() {
+ IRQ(Edge, ActiveHigh, Exclusive) {15}
+ Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
+ })
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0x0F)
+ }
+}