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| author | Zheng Bao <fishbaozi@gmail.com> | 2015-11-18 22:52:37 +0800 |
|---|---|---|
| committer | Zheng Bao <zheng.bao@amd.com> | 2015-11-18 17:02:28 +0100 |
| commit | 631c8a269006bb8f02860606d35f8d6590954f5e (patch) | |
| tree | bd7b6fb9c274ec1a807cbd55cd14eb169bcfd4c3 /src/mainboard/amd/bettong/dsdt.asl | |
| parent | 71c0aa29fa83219e76af70dd452b6b2e97e4dfbb (diff) | |
| download | coreboot-631c8a269006bb8f02860606d35f8d6590954f5e.tar.xz | |
AMD/Bettong: add FCH's GPIO, UART & I2C support
Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled
by registers mapped at MMIO space.
This ASL code is used for Windows drivers.
TEST:
1. Boot Windows 8 or Windows 10.
2. Install AMD Catalyst driver.
3. AMD FPIO, UART and I2C can be found in device manager.
4. I2C passed Multi Interface Test Tool (MITT) test.
Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11750
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd/bettong/dsdt.asl')
| -rw-r--r-- | src/mainboard/amd/bettong/dsdt.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl index 888d5cd292..2e6c96c567 100644 --- a/src/mainboard/amd/bettong/dsdt.asl +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -69,6 +69,9 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + /* Describe the devices in the Southbridge */ + #include "acpi/carrizo_fch.asl" + } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ |