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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-22 02:18:00 +0300
committerFelix Held <felix-coreboot@felixheld.de>2019-01-06 01:17:54 +0000
commitc70eed1e6202c928803f3e7f79161cd247a62b23 (patch)
treee46a6c87f6f13b7719fd40a9360d8d03359bfffb /src/mainboard/amd/bettong
parent54efaae701dacd58621e66a8cf56812eb5304946 (diff)
downloadcoreboot-c70eed1e6202c928803f3e7f79161cd247a62b23.tar.xz
device: Use pcidev_on_root()
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/amd/bettong')
-rw-r--r--src/mainboard/amd/bettong/BiosCallOuts.c2
-rw-r--r--src/mainboard/amd/bettong/mptable.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index 1ddcb1c123..c805015088 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -120,7 +120,7 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
int spdAddress;
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
UINT8 spdAddrLookup_rev_F [2][2][4]= {
{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
index e541c0ad3a..7c35f97c9b 100644
--- a/src/mainboard/amd/bettong/mptable.c
+++ b/src/mainboard/amd/bettong/mptable.c
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ struct device *dev = pcidev_on_root(0x14, 4);
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */