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authorElyes HAOUAS <ehaouas@noos.fr>2016-10-10 20:32:25 +0200
committerMartin Roth <martinroth@google.com>2016-10-21 19:43:33 +0200
commit8e641741377e2d11b23ced0a91d1e5cd66ed7434 (patch)
tree5b8e2b4a5e34de39191dac293c574c83ae4590d7 /src/mainboard/amd/db-ft3b-lc/OemCustomize.c
parenta8802577eae6e11a53ee2f697f880e36eebbe9b7 (diff)
downloadcoreboot-8e641741377e2d11b23ced0a91d1e5cd66ed7434.tar.xz
mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented code
Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16967 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/db-ft3b-lc/OemCustomize.c')
-rw-r--r--src/mainboard/amd/db-ft3b-lc/OemCustomize.c120
1 files changed, 60 insertions, 60 deletions
diff --git a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
index e8146a03d4..bffe88896a 100644
--- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
+++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
@@ -118,66 +118,66 @@ OemCustomizeInitEarly (
* use its default conservative settings.
*/
static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
+ /*
+ * The following macros are supported (use comma to separate macros):
+ *
+ * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ * The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ * AGESA will base on this value to disable unused MemClk to save power.
+ * Example:
+ * BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ * Bit AM3/S1g3 pin name
+ * 0 M[B,A]_CLK_H/L[0]
+ * 1 M[B,A]_CLK_H/L[1]
+ * 2 M[B,A]_CLK_H/L[2]
+ * 3 M[B,A]_CLK_H/L[3]
+ * 4 M[B,A]_CLK_H/L[4]
+ * 5 M[B,A]_CLK_H/L[5]
+ * 6 M[B,A]_CLK_H/L[6]
+ * 7 M[B,A]_CLK_H/L[7]
+ * And platform has the following routing:
+ * CS0 M[B,A]_CLK_H/L[4]
+ * CS1 M[B,A]_CLK_H/L[2]
+ * CS2 M[B,A]_CLK_H/L[3]
+ * CS3 M[B,A]_CLK_H/L[5]
+ * Then platform can specify the following macro:
+ * MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ *
+ * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ * The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ * AGESA will base on this value to tristate unused CKE to save power.
+ *
+ * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ * The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ * AGESA will base on this value to tristate unused ODT pins to save power.
+ *
+ * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ * The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ * AGESA will base on this value to tristate unused Chip select to save power.
+ *
+ * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ * Specifies the number of DIMM slots per channel.
+ *
+ * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ * Specifies the number of Chip selects per channel.
+ *
+ * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ * Specifies the number of channels per socket.
+ *
+ * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ * Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ *
+ * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ * Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ *
+ * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ * Byte6Seed, Byte7Seed, ByteEccSeed)
+ * Specifies the write leveling seed for a channel of a socket.
+ *
+ * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ * Byte6Seed, Byte7Seed, ByteEccSeed)
+ * Speicifes the HW RXEN training seed for a channel of a socket
+ */
#define SEED_WL 0x0E
WRITE_LEVELING_SEED(