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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-06-07 22:16:30 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-06-07 22:16:30 +0000 |
| commit | bc359473e23e4873b5f30f27680242fc939aa23b (patch) | |
| tree | 0fe3eb2ae3fbb731c90ea0b17a166fdddd139479 /src/mainboard/amd/db800/cache_as_ram_auto.c | |
| parent | 538b849695feccfd6a1419652de2608f0f5bdf1b (diff) | |
| download | coreboot-bc359473e23e4873b5f30f27680242fc939aa23b.tar.xz | |
Minor tweaks in the 440BX RAM init code (trivial).
Still hardcoded for Tyan S1846.
This slightly increases performance, but it's still pretty horrible.
Some RAM settings are causing a dramatically slow system (confirmed
by comparing memtest performance results of the proprietary BIOS
and our code). Haven't found the problem, yet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/db800/cache_as_ram_auto.c')
0 files changed, 0 insertions, 0 deletions