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authorUwe Hermann <uwe@hermann-uwe.de>2010-09-24 18:18:20 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-09-24 18:18:20 +0000
commitb015d02a857b27a65a3ef52839361236645754d2 (patch)
tree25f3b2b53a2d9dc4e91b1fd2004ed9454d325344 /src/mainboard/amd/dbm690t
parent8a6163e02b7fcbbeb0d3e88569a5df8bc3c7b072 (diff)
downloadcoreboot-b015d02a857b27a65a3ef52839361236645754d2.tar.xz
Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.
Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/dbm690t')
-rw-r--r--src/mainboard/amd/dbm690t/romstage.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 5988b75cd7..0fc2e43a6d 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -52,6 +52,11 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@@ -123,6 +128,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
+
+#if CONFIG_USBDEBUG
+ sb600_enable_usbdebug(0);
+ early_usbdebug_init();
+#endif
+
console_init();
/* Halt if there was a built in self test failure */