diff options
author | Kimarie Hoot <kimarie.hoot@se-eng.com> | 2013-03-07 17:12:36 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-20 05:54:28 +0100 |
commit | 2a9145e743ee9d10174c469a9fc1dad0ad75d73d (patch) | |
tree | 0118a7b15e155720ac9ac9f7a23b2b3eef869a6b /src/mainboard/amd/dinar/devicetree.cb | |
parent | b37ec540affaaeb3a8a230895c08778c54f1d076 (diff) | |
download | coreboot-2a9145e743ee9d10174c469a9fc1dad0ad75d73d.tar.xz |
AMD Dinar: Use SPD read code from F15 wrapper
Changes:
- Get rid of the dinar mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2777/
AMD Fam15: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
- select_socket() and restore_socket() were created from code that
was removed from AmdMemoryReadSPD() in dimmSpd.c. The functionality
is specific to the dinar mainboard configuration and was therefore
split from the generic read SPD functionality.
Change-Id: I1e4b9a20dc497c15dbde6d89865bd5ee7501cdc0
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/dinar/devicetree.cb')
-rw-r--r-- | src/mainboard/amd/dinar/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index e84762e0f0..09becd431f 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -97,6 +97,12 @@ chip northbridge/amd/agesa/family15/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 + }" end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex |