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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-02 20:08:35 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-23 05:30:42 +0200 |
| commit | 47b8075bb14de4dad4cfd2c2f42482e04644b28d (patch) | |
| tree | eabeb1e0762ee83cdeec20c4b1a01baee6563141 /src/mainboard/amd/dinar/devicetree.cb | |
| parent | 8b685398a74065d832fe2a3dfcfb313f0f4f11c3 (diff) | |
| download | coreboot-47b8075bb14de4dad4cfd2c2f42482e04644b28d.tar.xz | |
superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE
as argument instead of hard coding and playing funny business with the
pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6463
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/mainboard/amd/dinar/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/dinar/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 09becd431f..7a59fd29a3 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -85,7 +85,7 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x72 = 12 # PS/2 mouse interrupt end - end #SIO SMSC307 + end #SIO SMSC SCH4037 end #LPC device pci 14.4 on end # PCI bridge, 0x4384 device pci 14.5 on end # USB 3 |