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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-30 17:46:17 +0200
committerMartin Roth <martinroth@google.com>2016-08-14 19:06:25 +0200
commit8ab989e31561cea0c6af5d5e242dd2be97bc73b4 (patch)
tree31bc3a2175762b179d2fc093c34f62c18b15b9ee /src/mainboard/amd/dinar
parent589ef9de8faa2db11a7ce2769fc1d9396a82886b (diff)
downloadcoreboot-8ab989e31561cea0c6af5d5e242dd2be97bc73b4.tar.xz
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/dinar')
-rw-r--r--src/mainboard/amd/dinar/buildOpts.c4
-rw-r--r--src/mainboard/amd/dinar/romstage.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 3fd9c48885..e237ff0b79 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -54,10 +54,10 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-/* Select the cpu family. */
+/* Select the CPU family. */
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 70cd5e3586..bc5d3126f2 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");