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| author | Marc Jones <marcj303@gmail.com> | 2017-05-05 16:15:31 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:30 +0000 |
| commit | 2df118cdf04c72156ca92b940063288968ca7cea (patch) | |
| tree | fe3ed54c1cc3fffc69ca07f52bfbafd2a67f5fe4 /src/mainboard/amd/gardenia/mainboard.c | |
| parent | 1587dc8a2b4ddfe110cd0239c6506a320cccac96 (diff) | |
| download | coreboot-2df118cdf04c72156ca92b940063288968ca7cea.tar.xz | |
amd/gardenia: Switch to soc/amd/stoneyridge
Switch Garnenia mainboard to single soc/ directory structure.
Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/gardenia/mainboard.c')
| -rw-r--r-- | src/mainboard/amd/gardenia/mainboard.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index acc9b7cfb9..947029620c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <arch/acpi.h> #include <agesawrapper.h> -#include <southbridge/amd/common/amd_pci_util.h> +#include <amd_pci_util.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |