diff options
author | Mike Banon <mikebdp2@gmail.com> | 2020-02-13 16:20:08 +0000 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 13:58:16 +0000 |
commit | ebdf298ec2dd84810a37a4aac154200b2102b394 (patch) | |
tree | 58f2cba865d6ee46450d5d11fb9485c6f8d9659a /src/mainboard/amd/inagua/bootblock.c | |
parent | 24c1f94258d52402494f17f6e34cd489009c01f9 (diff) | |
download | coreboot-ebdf298ec2dd84810a37a4aac154200b2102b394.tar.xz |
mb/amd/inagua: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I55bf3004c728bb42ee51dfa917c58d97c56502cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38876
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/inagua/bootblock.c')
-rw-r--r-- | src/mainboard/amd/inagua/bootblock.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/amd/inagua/bootblock.c b/src/mainboard/amd/inagua/bootblock.c new file mode 100644 index 0000000000..78d8fca8f3 --- /dev/null +++ b/src/mainboard/amd/inagua/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <superio/smsc/kbc1100/kbc1100.h> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +void bootblock_mainboard_early_init(void) +{ + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} |