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author | Kimarie Hoot <kimarie.hoot@se-eng.com> | 2013-03-06 16:18:09 -0700 |
---|---|---|
committer | Martin Roth <martin.roth@se-eng.com> | 2013-03-08 22:33:57 +0100 |
commit | 31c5e07a04e90c03822d216d2dc92454b42e21ce (patch) | |
tree | c6501b0c4f63d9b6ae33809107c886fd001ccd16 /src/mainboard/amd/inagua/mainboard.c | |
parent | a5ddac02f40e2ebe5606ea65e5c22c63baa2c1c9 (diff) | |
download | coreboot-31c5e07a04e90c03822d216d2dc92454b42e21ce.tar.xz |
AMD Inagua: Use SPD read code from F14 wrapper
Changes:
- Get rid of the inagua mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2607
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/amd/inagua/mainboard.c')
-rw-r--r-- | src/mainboard/amd/inagua/mainboard.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 8907ebbfa7..8e92d6a62e 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -24,7 +24,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/sb800/sb800.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ void set_pcie_reset(void); @@ -79,6 +79,15 @@ static void mainboard_enable(device_t dev) /* Inagua mainboard specific setting */ set_pcie_dereset(); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = { |