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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 17:42:04 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-12 19:28:33 +0000 |
| commit | af258cc1791b5c46fcb13d41128cc99043a435be (patch) | |
| tree | 3c143244682d60fed4172086832ae9e4ad66fd76 /src/mainboard/amd/inagua/mainboard.c | |
| parent | cbbfb702f693c1bbaf83a9d3d8a3c0caabda1814 (diff) | |
| download | coreboot-af258cc1791b5c46fcb13d41128cc99043a435be.tar.xz | |
mb/*/*: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/amd/inagua/mainboard.c')
| -rw-r--r-- | src/mainboard/amd/inagua/mainboard.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 83fe394be7..47a267b323 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -16,7 +16,6 @@ #include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ static void init_gpios(void) { @@ -34,16 +33,15 @@ static void init_gpios(void) /* Multi-function pins switch to GPIO0-35, these pins are shared with * PCI pins, make sure Hudson PCI device is disabled. */ - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1); + pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1); /* select IOMux to function1/2, corresponds to GPIO */ - RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1); - RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2); - + iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1); + iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2); /* output low */ - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48); - RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48); + gpio_100_write8(0x20, 0x48); + gpio_100_write8(0x32, 0x48); } |