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authorKerry Sheh <shekairui@gmail.com>2011-12-22 12:18:37 +0800
committerMarc Jones <marcj303@gmail.com>2012-01-02 23:10:05 +0100
commitd6ed09b7eca40a29a2cd4a3b6a5f0e4dfeb07641 (patch)
treecfb7cdd2c2252d5767ab58340ef9a518a3671a27 /src/mainboard/amd/inagua
parenta4f06f183b56cbcd00e0559c1d6c493fed4d7894 (diff)
downloadcoreboot-d6ed09b7eca40a29a2cd4a3b6a5f0e4dfeb07641.tar.xz
F14 mainboard: update acpi interrupt routing in pic and apic mode
Add interrupt routing for APU GNB internal Graphic and HD audio device, and other pcie bridge device in GNB. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/452 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/inagua')
-rw-r--r--src/mainboard/amd/inagua/acpi/routing.asl59
1 files changed, 34 insertions, 25 deletions
diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl
index cb5039425f..d7e4687b18 100644
--- a/src/mainboard/amd/inagua/acpi/routing.asl
+++ b/src/mainboard/amd/inagua/acpi/routing.asl
@@ -31,22 +31,28 @@ Scope(\_SB) {
/* NB devices */
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ Package(){0x0001FFFF, 0, INTC, 0 },
+ Package(){0x0001FFFF, 1, INTD, 0 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, INTB, 0 }, */
- /* Package(){0x0005FFFF, 1, INTC, 0 }, */
- /* Package(){0x0005FFFF, 2, INTD, 0 }, */
- /* Package(){0x0005FFFF, 3, INTA, 0 }, */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
Package(){0x0006FFFF, 0, INTC, 0 },
Package(){0x0006FFFF, 1, INTD, 0 },
@@ -126,41 +132,44 @@ Scope(\_SB) {
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
Package(){0x0003FFFF, 0, 0, 19 },
+ Package(){0x0003FFFF, 1, 0, 16 },
+ Package(){0x0003FFFF, 2, 0, 17 },
+ Package(){0x0003FFFF, 3, 0, 18 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, 0, 16 },
- /* Package(){0x0004FFFF, 1, 0, 17 }, */
- /* Package(){0x0004FFFF, 2, 0, 18 }, */
- /* Package(){0x0004FFFF, 3, 0, 19 }, */
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- /* Package(){0x0005FFFF, 0, 0, 17 }, */
- /* Package(){0x0005FFFF, 1, 0, 18 }, */
- /* Package(){0x0005FFFF, 2, 0, 19 }, */
- /* Package(){0x0005FFFF, 3, 0, 16 }, */
+ Package(){0x0005FFFF, 0, 0, 17 },
+ Package(){0x0005FFFF, 1, 0, 18 },
+ Package(){0x0005FFFF, 2, 0, 19 },
+ Package(){0x0005FFFF, 3, 0, 16 },
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- /* Package(){0x0006FFFF, 0, 0, 18 }, */
- /* Package(){0x0006FFFF, 1, 0, 19 }, */
- /* Package(){0x0006FFFF, 2, 0, 16 }, */
- /* Package(){0x0006FFFF, 3, 0, 17 }, */
+ Package(){0x0006FFFF, 0, 0, 18 },
+ Package(){0x0006FFFF, 1, 0, 19 },
+ Package(){0x0006FFFF, 2, 0, 16 },
+ Package(){0x0006FFFF, 3, 0, 17 },
/* Bus 0, Dev 7 - PCIe Bridge for network card */
- /* Package(){0x0007FFFF, 0, 0, 19 }, */
- /* Package(){0x0007FFFF, 1, 0, 16 }, */
- /* Package(){0x0007FFFF, 2, 0, 17 }, */
- /* Package(){0x0007FFFF, 3, 0, 18 }, */
+ Package(){0x0007FFFF, 0, 0, 19 },
+ Package(){0x0007FFFF, 1, 0, 16 },
+ Package(){0x0007FFFF, 2, 0, 17 },
+ Package(){0x0007FFFF, 3, 0, 18 },
/* Bus 0, Dev 9 - PCIe Bridge for network card */
Package(){0x0009FFFF, 0, 0, 17 },
- /* Package(){0x0009FFFF, 1, 0, 16 }, */
- /* Package(){0x0009FFFF, 2, 0, 17 }, */
- /* Package(){0x0009FFFF, 3, 0, 18 }, */
+ Package(){0x0009FFFF, 1, 0, 16 },
+ Package(){0x0009FFFF, 2, 0, 17 },
+ Package(){0x0009FFFF, 3, 0, 18 },
/* Bus 0, Dev A - PCIe Bridge for network card */
Package(){0x000AFFFF, 0, 0, 18 },
- /* Package(){0x000AFFFF, 1, 0, 16 }, */
- /* Package(){0x000AFFFF, 2, 0, 17 }, */
- /* Package(){0x000AFFFF, 3, 0, 18 }, */
+ Package(){0x000AFFFF, 1, 0, 16 },
+ Package(){0x000AFFFF, 2, 0, 17 },
+ Package(){0x000AFFFF, 3, 0, 18 },
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices in APIC mode */