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authorKerry Sheh <shekairui@gmail.com>2011-12-22 12:18:26 +0800
committerMarc Jones <marcj303@gmail.com>2012-01-02 23:13:50 +0100
commit28f171096bc289f848c03593a6d04c2987c89617 (patch)
tree86adffc82f7120ac3be7ca426a5b5e5b7f170465 /src/mainboard/amd/inagua
parentd6ed09b7eca40a29a2cd4a3b6a5f0e4dfeb07641 (diff)
downloadcoreboot-28f171096bc289f848c03593a6d04c2987c89617.tar.xz
F14 mainboard: mptable update
Add GNB internal graphic interrupt, correct southbridge hd audio device interrupt. and remove the dead code already commented out. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/451 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/inagua')
-rw-r--r--src/mainboard/amd/inagua/mptable.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 7278936902..73d946ccd5 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -166,11 +166,15 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ /* Southbridge HD Audio */
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
@@ -179,7 +183,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);