Leverage the Pstate table created by AGESA.

The name of processor created by AGESA is P00n, whose P is
BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
from 0. The dsdt should be aligned with that.
This feature has only been tested on persimmon. The changes on all the
other boards were propagated.

Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/884
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

3 files changed, 21 insertions, 86 deletions

diff --git a/src/mainboard/amd/inagua/acpi/cpstate.asl b/src/mainboard/amd/inagua/acpi/cpstate.asl
deleted file mode 100644
index 5eca9cc5c7..0000000000
--- a/src/mainboard/amd/inagua/acpi/cpstate.asl
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* This file defines the processor and performance state capability
- * for each core in the system.  It is included into the DSDT for each
- * core.  It assumes that each core of the system has the same performance
- * characteristics.
-*/
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
-	{
-		Scope (\_PR) {
-		Processor(CPU0,0,0x808,0x06) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU1,1,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU2,2,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU3,3,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-	}
-*/
-	/* P-state support: The maximum number of P-states supported by the */
-	/* CPUs we'll use is 6. */
-	/* Get from AMI BIOS. */
-	Name(_PSS, Package(){
-		Package ()
-		{
-		    0x00000AF0,
-		    0x0000BF81,
-		    0x00000002,
-		    0x00000002,
-		    0x00000000,
-		    0x00000000
-		},
-
-		Package ()
-		{
-		    0x00000578,
-		    0x000076F2,
-		    0x00000002,
-		    0x00000002,
-		    0x00000001,
-		    0x00000001
-		}
-	})
-
-	Name(_PCT, Package(){
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
-	})
-
-	Method(_PPC, 0){
-		Return(0)
-	}
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 3b8bd39adf..ff3b7dbf5d 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -264,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start)
 		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
 	}
 
-#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	/* The DSDT needs additional work for the AGESA SSDT Pstate table */
+	/* Keep the comment for a while. */
 	current = (current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
@@ -273,12 +274,9 @@ unsigned long write_acpi_tables(unsigned long start)
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
 		acpi_add_table(rsdp,ssdt);
-	}
-	else {
+	} else {
 		printk(BIOS_DEBUG, "  AGESA SSDT Pstate table NULL. Skipping.\n");
 	}
-	acpi_add_table(rsdp,ssdt);
-#endif
 
 	current = (current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
index 361adbbbb0..77086766cd 100644
--- a/src/mainboard/amd/inagua/dsdt.asl
+++ b/src/mainboard/amd/inagua/dsdt.asl
@@ -64,21 +64,33 @@ DefinitionBlock (
 	 */
 	Scope (\_PR) {		/* define processor scope */
 		Processor(
-			CPU0,		/* name space name */
+			C000,		/* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
 			0,		/* Unique number for this processor */
-			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x810,		/* PBLK system I/O address !hardcoded! */
 			0x06		/* PBLKLEN for boot processor */
 			) {
-			#include "acpi/cpstate.asl"
 		}
 
 		Processor(
-			CPU1,		/* name space name */
+			C001,		/* name space name */
 			1,		/* Unique number for this processor */
-			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x810		,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			C002,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x810		,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+		}
+		Processor(
+			C003,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x810		,		/* PBLK system I/O address !hardcoded! */
 			0x00		/* PBLKLEN for boot processor */
 			) {
-			#include "acpi/cpstate.asl"
 		}
 	} /* End _PR scope */