mb/*/*: use ACPIMMIO common block wherever possible

TEST=boot PC Engines apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

2 files changed, 90 insertions, 102 deletions

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index b6267a69bb..0ae9f28f98 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -46,76 +47,68 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 	UINT32            AcpiMmioAddr;
 	UINT32            GpioMmioAddr;
 	UINT8             Data8;
-	UINT16            Data16;
 	UINT8             TempData8;
 
 	FcnData = Data;
 	MemData = ConfigPtr;
 
 	Status  = AGESA_SUCCESS;
-	/* Get SB MMIO Base (AcpiMmioAddr) */
-	WriteIo8 (0xCD6, 0x27);
-	Data8   = ReadIo8(0xCD7);
-	Data16  = Data8 << 8;
-	WriteIo8 (0xCD6, 0x26);
-	Data8   = ReadIo8(0xCD7);
-	Data16  |= Data8;
-	AcpiMmioAddr = (UINT32)Data16 << 16;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 
 	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
 	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
 	Data8 |= BIT2+BIT3;
 	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
 	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
 	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
 	Data8 |= BIT2+BIT3;
 	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
 	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
 	switch (MemData->ParameterListPtr->DDR3Voltage) {
-		case VOLT1_35:
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-			Data8 |= (UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-			break;
-		case VOLT1_25:
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-			break;
-		case VOLT1_5:
-		default:
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-			Data8 |= (UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	case VOLT1_35:
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
 	}
 	return Status;
 }
@@ -130,70 +123,67 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	UINT32  GpioMmioAddr;
 	UINT32  AcpiMmioAddr;
 	UINT8   Data8;
-	UINT16  Data16;
 
 	FcnData   = Data;
 	ResetInfo = ConfigPtr;
-	// Get SB800 MMIO Base (AcpiMmioAddr)
-	WriteIo8(0xCD6, 0x27);
-	Data8 = ReadIo8(0xCD7);
-	Data16 = Data8 << 8;
-	WriteIo8(0xCD6, 0x26);
-	Data8 = ReadIo8(0xCD7);
-	Data16 |= Data8;
-	AcpiMmioAddr = (UINT32)Data16 << 16;
-	Status = AGESA_UNSUPPORTED;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-	switch (ResetInfo->ResetId)
-	{
-		case 4:
-			switch (ResetInfo->ResetControl) {
-				case AssertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-					Data8 &= ~(UINT8)BIT6;
-					Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-					Status = AGESA_SUCCESS;
-					break;
-				case DeassertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-					Data8 |= BIT6;
-					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-					Status = AGESA_SUCCESS;
-					break;
-			}
+	Status = AGESA_UNSUPPORTED;
+	switch (ResetInfo->ResetId) {
+	case 4:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 &= ~(UINT8)BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 |= BIT6;
+			/* MXM_GPIO0. GPIO21 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Status = AGESA_SUCCESS;
 			break;
-		case 6:
-			switch (ResetInfo->ResetControl) {
-				case AssertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-					Data8 &= ~(UINT8)BIT6;
-					Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-					Status = AGESA_SUCCESS;
-					break;
-				case DeassertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-					Data8 |= BIT6;
-					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-					Status = AGESA_SUCCESS;
-					break;
-			}
+		}
+		break;
+	case 6:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 &= ~(UINT8)BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
 			break;
-		case 7:
-			switch (ResetInfo->ResetControl) {
-				case AssertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-					Data8 &= ~(UINT8)BIT6;
-					Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-					Status = AGESA_SUCCESS;
-					break;
-				case DeassertSlotReset:
-					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-					Data8 |= BIT6;
-					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-					Status = AGESA_SUCCESS;
-					break;
-			}
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 |= BIT6;
+			/* PCIE_RST#_LAN, GPIO25 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Status = AGESA_SUCCESS;
 			break;
+		}
+		break;
+	case 7:
+		switch (ResetInfo->ResetControl) {
+		case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 &= ~(UINT8)BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 |= BIT6;
+			/* MPCIE_RST0, GPIO02 */
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
 	}
-	return  Status;
+	return Status;
 }
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 83fe394be7..47a267b323 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -16,7 +16,6 @@
 #include <amdblocks/acpimmio.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>	/* Platform Specific Definitions */
 
 static void init_gpios(void)
 {
@@ -34,16 +33,15 @@ static void init_gpios(void)
 	/* Multi-function pins switch to GPIO0-35, these pins are shared with
 	 * PCI pins, make sure Hudson PCI device is disabled.
 	 */
-	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
 
 	/* select IOMux to function1/2, corresponds to GPIO */
-	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
-	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
-
+	iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
+	iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
 
 	/* output low */
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
-	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
+	gpio_100_write8(0x20, 0x48);
+	gpio_100_write8(0x32, 0x48);
 }