mb/amd/lamar: Drop unmaintained ROMCC board

Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 0 insertions, 101 deletions

diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb
deleted file mode 100644
index 5c88a3c557..0000000000
--- a/src/mainboard/amd/lamar/devicetree.cb
+++ /dev/null
@@ -1,101 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012        Advanced Micro Devices, Inc.
-#               2013 - 2014 Sage Electronic Engineering, LLC
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/pi/00630F01/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/pi/00630F01
-		  device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-
-		chip northbridge/amd/pi/00630F01
-			device pci 0.0 on end   # 0x1422 Root Complex
-			device pci 0.2 off end  # 0x1423 IOMMU
-			device pci 1.0 on end   # 0x13XX Internal Graphics
-			device pci 1.1 on end   # 0x1308 DisplayPort/HDMI Audio
-			device pci 2.0 on end   # 0x1424 GFX PCIe Host Bridge
-			device pci 2.1 on end   # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119)
-			device pci 2.2 off end  # 0x1425 P2P Bridge for GFX PCIe Port 1
-			device pci 3.0 on end   # 0x1424 GPP PCIe Host Bridge
-			device pci 3.1 on end   # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118)
-			device pci 3.2 on end   # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120)
-			device pci 3.3 off end  # 0x1426 P2P Bridge for GPP PCIe Port 2
-			device pci 3.4 off end  # 0x1426 P2P Bridge for GPP PCIe Port 3
-			device pci 3.5 off end  # 0x1426 P2P Bridge for GPP PCIe Port 4
-			device pci 4.0 on end   # 0x1424 UMI PCIe Host Bridge
-#				device pci 4.1 on end   # 0x1426 P2P bridge for UMI link
-#				device pci 4.2 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 3
-#				device pci 4.3 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 2
-#				device pci 4.4 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 1
-#				device pci 4.5 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 0
-		end	#chip northbridge/amd/pi/00630F01
-
-		chip southbridge/amd/pi/hudson
-			device pci 10.0 on end  # 0x7814 XHCI HC0
-			device pci 10.1 on end  # 0x7814 XHCI HC1
-			device pci 11.0 on end  # 0x7800-0x7805 SATA (device ID depends on mode)
-			device pci 12.0 on end  # 0x7807 USB OHCI
-			device pci 12.2 on end  # 0x7808 USB EHCI
-			device pci 13.0 on end  # 0x7807 USB OHCI
-			device pci 13.2 on end  # 0x7808 USB EHCI
-			device pci 14.0 on end  # SM
-			device pci 14.1 on end  # 0x780C IDE
-			device pci 14.2 on end  # 0x780D HDA
-			device pci 14.3 on      # 0x780E LPC
-				chip superio/fintek/f81216h
-					register "conf_key_mode" = "0x77"
-					device pnp 4e.0 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.1 on			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 4e.2 off end		# COM3
-					device pnp 4e.3 off end		# COM4
-					device pnp 4e.8 off end		# WDT
-				end # f81865f
-			end #LPC
-			device pci 14.4 on end  # 0x780F PCI :: PCI-b conflict with GPIO.
-			device pci 14.5 on end  # 0x7809 USB OHCI
-			device pci 14.7 on end  # 0x7806 SD Flash Controller
-			device pci 15.0 on end  # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller)
-			device pci 15.1 on end  # 0x43A1 SB GPP Port 1 (mPCIe slot J122)
-			device pci 15.2 on end  # 0x43A2 SB GPP Port 2 (mPCIe slot J123)
-			device pci 15.3 off end # 0x43A3 SB GPP Port 3
-				register "gpp_configuration" = "4"
-			device pci 16.0 on end  # 0x7809 USB OHCI (when the xHCI device is disabled)
-		end	#southbridge/amd/pi/hudson
-
-		chip northbridge/amd/pi/00630F01
-			device pci 18.0 on end # 0x141A HT Configuration
-			device pci 18.1 on end # 0x141B Address Maps
-			device pci 18.2 on end # 0x141C DRAM Configuration
-			device pci 18.3 on end # 0x141D Miscellaneous
-			device pci 18.4 on end # 0x141E Power Management
-			device pci 18.5 on end # 0x141F Northbridge
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end
-
-	end #domain
-end #northbridge/amd/pi/00630F01/root_complex