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author | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-06-10 05:10:19 -0600 |
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committer | Dave Frodin <dave.frodin@se-eng.com> | 2015-04-23 00:58:26 +0200 |
commit | 72645bbd67cf89411c05c956ef824e96fefb5d84 (patch) | |
tree | 339345a8ff4c9a36b0cd9d56ad7cff8ddac052ea /src/mainboard/amd/lamar/romstage.c | |
parent | 0dff57dd7ab9e4863d464f54f68dbd75a8f4d96a (diff) | |
download | coreboot-72645bbd67cf89411c05c956ef824e96fefb5d84.tar.xz |
AMD Lamar: Add a new AMD FP3 socket mainboard
Add a new mainboard based on AMD's Family 15 Model 30 processor.
TEST: Lamar will boot DOS, Ubuntu 14.10 and Windows 7.
Change-Id: I2f73c396247239d54f978846e8958950697d7464
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5968
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/amd/lamar/romstage.c')
-rw-r--r-- | src/mainboard/amd/lamar/romstage.c | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c new file mode 100644 index 0000000000..776da83599 --- /dev/null +++ b/src/mainboard/amd/lamar/romstage.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/s3_resume.h> +#include "cbmem.h" +#include "superio/fintek/f81216h/f81216h.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + amd_initmmio(); + hudson_lpc_decode(); + + outb(0x24, 0xCD6); + outb(0x01, 0xCD7); + *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ + *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ + + hudson_lpc_port80(); + + if (!cpu_init_detectedx) { + post_code(0x30); + f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + post_code(0x38); + printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); + } + else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +} |