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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-21 17:09:31 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-23 13:47:39 +0000 |
| commit | 86db2c74ffc38ad6ca92c62f0fb2858a2423c089 (patch) | |
| tree | 546f8cc26eda84d97d2eff47c07defebe9393db4 /src/mainboard/amd/mandolin | |
| parent | a19d98647b0b1862c28b362505b30f4551b2fe2c (diff) | |
| download | coreboot-86db2c74ffc38ad6ca92c62f0fb2858a2423c089.tar.xz | |
amd/picasso: rename PCIe descriptor to DXIO descriptor
Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.
Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/mandolin')
| -rw-r--r-- | src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c index 3625554a42..47e9aad52f 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c +++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c @@ -4,7 +4,7 @@ #include <soc/soc_util.h> #include <types.h> -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { { /* MXM */ .port_present = true, .engine_type = PCIE_ENGINE, @@ -94,7 +94,7 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { } }; -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { { /* MXM */ .port_present = true, .engine_type = PCIE_ENGINE, @@ -198,18 +198,18 @@ static const fsp_ddi_descriptor dali_ddi_descriptors[] = { } }; -void mainboard_get_pcie_ddi_descriptors( - const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { if (soc_is_reduced_io_sku()) { /* Dali */ - *pcie_descs = dali_pcie_descriptors; - *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); + *dxio_descs = dali_dxio_descriptors; + *dxio_num = ARRAY_SIZE(dali_dxio_descriptors); *ddi_descs = dali_ddi_descriptors; *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); } else { /* Picasso and default */ - *pcie_descs = pco_pcie_descriptors; - *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); + *dxio_descs = pco_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pco_dxio_descriptors); *ddi_descs = pco_ddi_descriptors; *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); } |