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author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-02-09 10:22:33 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-09 10:22:33 +0000 |
commit | e30db0e37034f6698eced00727b6ad0ba3fc5c7b (patch) | |
tree | 8bfb03dcb7f3b161772f1099bd62240463684d4d /src/mainboard/amd/norwich/romstage.c | |
parent | 37d8c215a27f3c7938e921ccb849a9b8fa01be77 (diff) | |
download | coreboot-e30db0e37034f6698eced00727b6ad0ba3fc5c7b.tar.xz |
Port of CS5536 early UART setup from v3.
Permit early setup of COM2
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/norwich/romstage.c')
-rw-r--r-- | src/mainboard/amd/norwich/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index fc7e96b342..19c5b17ade 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -115,7 +115,7 @@ void cache_as_ram_main(void) * up later... */ /* If debug. real setup done in chipset init via Config.lb. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); mb_gpio_init(); uart_init(); console_init(); |