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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-02-09 16:07:41 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-02-13 21:56:38 +0100 |
| commit | 7916f4cef62bf032af86368a9df45db833d09b79 (patch) | |
| tree | ab2a85208db187624f8615c135acf605777fc7d8 /src/mainboard/amd/norwich | |
| parent | 50759ed4ff438db6f3b093984fbb79d6445ebcb3 (diff) | |
| download | coreboot-7916f4cef62bf032af86368a9df45db833d09b79.tar.xz | |
AMD Geode cpus: apply un-written naming rules
Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.
Rename directories and Kconfig as follows:
model_lx -> geode_lx
model_gx1 -> geode_gx1
model_gx2 -> geode_gx2
Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/norwich')
| -rw-r--r-- | src/mainboard/amd/norwich/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/norwich/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/norwich/romstage.c | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig index b265eeb103..dec8e01d34 100644 --- a/src/mainboard/amd/norwich/Kconfig +++ b/src/mainboard/amd/norwich/Kconfig @@ -3,7 +3,7 @@ if BOARD_AMD_NORWICH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index 533ea92b2d..b2ede77ed1 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 097965f3b1..d8fca5a51f 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -46,9 +46,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { |