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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-21 12:32:43 +0300 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-26 08:36:05 +0000 |
commit | e52738b42889a8bf6b96fe86b87fbdd73947b367 (patch) | |
tree | ab3ddcc914b9ab69fdb793ba42e30480d9a8824f /src/mainboard/amd/olivehill/OemCustomize.c | |
parent | e1dced4561ed3b7bff98984c1d51b8e84f004b47 (diff) | |
download | coreboot-e52738b42889a8bf6b96fe86b87fbdd73947b367.tar.xz |
AGESA binaryPI boards: Fix some whitespace
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/amd/olivehill/OemCustomize.c')
-rw-r--r-- | src/mainboard/amd/olivehill/OemCustomize.c | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index d8171adb7b..0edbf5eb3f 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -21,11 +21,11 @@ #include <northbridge/amd/agesa/state_machine.h> -static const PCIe_PORT_DESCRIPTOR PortList [] = { +static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -34,8 +34,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -44,8 +44,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -54,8 +54,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -64,8 +64,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -73,24 +73,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { } }; -static const PCIe_DDI_DESCRIPTOR DdiList [] = { +static const PCIe_DDI_DESCRIPTOR DdiList[] = { /* DP0 to HDMI0/DP */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) }, /* DP1 to FCH */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) }, /* DP2 to HDMI1/DP */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) }, }; @@ -167,14 +167,14 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A), - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS (LAYERS_4), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS(LAYERS_4), - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), PSO_END }; |