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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 11:03:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 05:49:09 +0100
commit59e03342076ea79cb7c0ed2fdbd199947c8c5212 (patch)
treeec951913b7ad95c35faced30b4dadc6413619b5d /src/mainboard/amd/olivehill
parent7d09cfcf749c1c0fd1c3791585065b39ec1a3433 (diff)
downloadcoreboot-59e03342076ea79cb7c0ed2fdbd199947c8c5212.tar.xz
AGESA: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/amd/olivehill')
-rw-r--r--src/mainboard/amd/olivehill/romstage.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index b1addb3db3..bb1ad30f7f 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
* even though the register is not documented in the Kabini BKDG.
@@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);