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authorBruce Griffith <Bruce.Griffith@se-eng.com>2014-08-15 12:38:21 -0600
committerBruce Griffith <Bruce.Griffith@se-eng.com>2014-09-04 23:53:56 +0200
commit79f47cf8c0c54848ee13b727482ff8936a68e1f5 (patch)
tree1216e022d1eca8ca86eaea545e006f9397e99a3f /src/mainboard/amd/olivehillplus/acpi
parent3c12cb03847d2db41809ae434530782a7dbef48b (diff)
downloadcoreboot-79f47cf8c0c54848ee13b727482ff8936a68e1f5.tar.xz
mainboard: Add AMD DB-FT3b (Olive Hill+) with Steppe Eagle SoC
Create a new mainboard based on the AMD DB-FT3 development board (Olive Hill) using an AMD Steppe Eagle processor. The actual DB-FT3 and DB-FT3b mainboards are identical except for the soldered-down SoC device. The new AMD DB-FT3b development board (Olive Hill+) features: * Mini-ITX form factor * 2x DisplayPort * 1x VGA * Integrated Realtek RTL8111-compatible Ethernet * 2x USB 3.0 ports * 2x USB 2.0 externally-accessible ports * 2x USB 2.0 internally-accessible ports (via headers) * micro LPC header * Integrated platform security processor * 2x Full-size DDR3 DIMM support (1 channel) * Realtek ALC272 HD audio * 2x SATA ports * 1x SD card slot * 1x PCIe (x4) slot * 1x mini-PCIe slot * 8-pin programming header Eliminate the extraneous headers included in PlatformGnbPcie. BiosCallOuts normally has a bunch of extraneous references to the mainboard name. Rather than correct the spelling of a bunch of instances, just get rid of them. For the most part, use the Olive Hill ACPI definitions since the DB-FT3b board ("Olive Hill+") and Olive Hill are the same board with different processors. Change some function prototypes for functions without parameters to void instead of AGESA's VOID. There are no parameters for these functions, so there is no real reason to use VOID. S3 and fan control are not supported. HD audio is not working. Change-Id: I794d7a8f4f948346cfe7cbd443c9aed5f70c99ed Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6681 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/amd/olivehillplus/acpi')
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/AmdImc.asl113
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/gpe.asl78
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/ide.asl1
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/mainboard.asl41
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/routing.asl197
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/sata.asl1
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/si.asl27
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/sleep.asl97
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/superio.asl1
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/thermal.asl1
-rw-r--r--src/mainboard/amd/olivehillplus/acpi/usb_oc.asl41
11 files changed, 598 insertions, 0 deletions
diff --git a/src/mainboard/amd/olivehillplus/acpi/AmdImc.asl b/src/mainboard/amd/olivehillplus/acpi/AmdImc.asl
new file mode 100644
index 0000000000..8ff4b1ceb5
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/AmdImc.asl
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl
new file mode 100644
index 0000000000..8d4f8a2159
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/gpe.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/olivehillplus/acpi/ide.asl b/src/mainboard/amd/olivehillplus/acpi/ide.asl
new file mode 100644
index 0000000000..95d1db41b8
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/ide.asl
@@ -0,0 +1 @@
+/* No IDE functionality */
diff --git a/src/mainboard/amd/olivehillplus/acpi/mainboard.asl b/src/mainboard/amd/olivehillplus/acpi/mainboard.asl
new file mode 100644
index 0000000000..05523fb19a
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/mainboard.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+ Field(GP0B, ByteAcc, NoLock, Preserve) {
+ , 11,
+ USBS, 1,
+}
diff --git a/src/mainboard/amd/olivehillplus/acpi/routing.asl b/src/mainboard/amd/olivehillplus/acpi/routing.asl
new file mode 100644
index 0000000000..91849ed353
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/routing.asl
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 44 },
+ Package(){0x0001FFFF, 1, 0, 45 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+})
+
+Name(PS2, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS2, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GFX */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+})
+
+/* GPP 0 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+})
+
+/* GPP 1 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+})
+
+/* GPP 2 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+})
+
+/* GPP 3 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+})
diff --git a/src/mainboard/amd/olivehillplus/acpi/sata.asl b/src/mainboard/amd/olivehillplus/acpi/sata.asl
new file mode 100644
index 0000000000..f675323ded
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/sata.asl
@@ -0,0 +1 @@
+/* No SATA functionality */
diff --git a/src/mainboard/amd/olivehillplus/acpi/si.asl b/src/mainboard/amd/olivehillplus/acpi/si.asl
new file mode 100644
index 0000000000..3cc2170591
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/si.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/amd/olivehillplus/acpi/sleep.asl b/src/mainboard/amd/olivehillplus/acpi/sleep.asl
new file mode 100644
index 0000000000..aa22879e83
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/sleep.asl
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+*s Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ \_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ Store(1,USBS)
+
+ \_SB.AWAK(Arg0)
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/olivehillplus/acpi/superio.asl b/src/mainboard/amd/olivehillplus/acpi/superio.asl
new file mode 100644
index 0000000000..69c610802c
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/superio.asl
@@ -0,0 +1 @@
+/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/amd/olivehillplus/acpi/thermal.asl b/src/mainboard/amd/olivehillplus/acpi/thermal.asl
new file mode 100644
index 0000000000..edb1daf84b
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/thermal.asl
@@ -0,0 +1 @@
+/* No thermal zone functionality */
diff --git a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl b/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl
new file mode 100644
index 0000000000..8dae1df159
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+