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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-10-21 18:22:32 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-11-20 19:02:37 +0100
commite4c17ce8036ae247f5e73c37789a9181e7cbd3c7 (patch)
tree47f6bd7cb995f7c1c33a8e4bc52034cee3b3471d /src/mainboard/amd/olivehillplus/dsdt.asl
parent84693d3dd40bdb291ec8dd92f99a4349da0db62b (diff)
downloadcoreboot-e4c17ce8036ae247f5e73c37789a9181e7cbd3c7.tar.xz
AMD: Isolate AGESA and PI build environments
To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7149 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd/olivehillplus/dsdt.asl')
-rw-r--r--src/mainboard/amd/olivehillplus/dsdt.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
index 15bcd3dfa4..b74dac6218 100644
--- a/src/mainboard/amd/olivehillplus/dsdt.asl
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -40,7 +40,7 @@ DefinitionBlock (
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
- #include <cpu/amd/agesa/00730F01/acpi/cpu.asl>
+ #include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
@@ -65,7 +65,7 @@ DefinitionBlock (
Device(PCI0) {
/* Describe the AMD Northbridge */
- #include <northbridge/amd/agesa/00730F01/acpi/northbridge.asl>
+ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>