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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-29 06:37:52 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-30 05:59:41 +0000
commitaeb85d53e90728bf758b08895c7ed5dbf9cf3062 (patch)
tree175923e7e2483ed3678e7fadf5a7939450cf8c04 /src/mainboard/amd/olivehillplus
parent34ac1ab4a3172fc821e47824f107873da25d8991 (diff)
downloadcoreboot-aeb85d53e90728bf758b08895c7ed5dbf9cf3062.tar.xz
binaryPI: Clean leftover romstage prototype
Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/olivehillplus')
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6df12e31cc..519825827a 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -19,12 +19,11 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
{
u32 val;