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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-21 12:19:25 +0200
committerMartin Roth <martinroth@google.com>2016-08-23 15:46:03 +0200
commite53e488cf118ce4842fc31fbf38529f22053333c (patch)
tree6d12329b9b85ce3640959175ee36d38cd15c95bd /src/mainboard/amd/olivehillplus
parent0638b60590731a9cf3b1200ec6a1bc185085eb6c (diff)
downloadcoreboot-e53e488cf118ce4842fc31fbf38529f22053333c.tar.xz
src/mainboard: Remove unnecessary whitespace before "\n"
Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16283 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/olivehillplus')
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index a5c529e7c5..6d1e4ea31f 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -65,8 +65,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Load MPB */
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/*
* This refers to LpcClkDrvSth settling time. Without this setting, processor